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| features ? single 2.7v - 3.6v supply ? serial peripheral interface (spi) compatible ? supports spi modes 0 and 3 ? supports rapids operation ? supports dual- and quad-input program ? supports dual- and quad-output read ? very high operating frequencies ? 100 mhz for rapids ? 85 mhz for spi ? clock-to-output (t v ) of 5 ns maximum ? flexible, optimized erase architecture for code + data storage applications ? uniform 4-kbyte block erase ? uniform 32-kbyte block erase ? uniform 64-kbyte block erase ? full chip erase ? individual sector protection with global protect/unprotect feature ? 64 sectors of 64-kbytes each ? hardware controlled locking of protected sectors via wp pin ? sector lockdown ? make any combination of 64-kbyte sectors permanently read-only ? 128-byte programmable otp security register ? flexible programming ? byte/page program (1 to 256 bytes) ? fast program and erase times ? 1.5 ms typical page program (256 bytes) time ? 50 ms typical 4-kbyte block erase time ? 250 ms typical 32-kbyte block erase time ? 400 ms typical 64-kbyte block erase time ? program and erase suspend/resume ? automatic checking and reporting of erase/program failures ? software controlled reset ? jedec standard manufacturer and device id read methodology ? low power dissipation ? 7 ma active read current (typical at 20 mhz) ? 5 a deep power-down current (typical) ? endurance: 100,000 program/erase cycles ? data retention: 20 years ? complies with full industrial temperature range ? industry standard green (pb/halide-free/rohs compliant) package options ? 8-lead soic (150-mil and 208-mil wide) ? 16-lead soic (300-mil wide) ? 8-pad very thin dfn ( 5x6x0.6mm) 32-megabit 2.7-volt minimum spi serial flash memory with dual-i/o and quad-i/o support at25dq321a preliminary 8718a?dflash?04/10
2 8718a?dflash?04/10 at25dq321a [preliminary] 1. description the at25dq321a is a serial interface flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from flash memory into embedded or external ram for execution. the flexible erase architecture of the at25dq321a, with its erase granularity as small as 4- kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage eeprom devices. the physical sectoring and the erase block sizes of the at25dq321a have been optimized to meet the needs of today's code and data storage applications. by optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase flash memory devices can be greatly reduced. this increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. the at25dq321a also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. by providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. this is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. in addition to individual sector protection capabilities, the at25dq321a incorporates global protect and global unprotect features that allow the entire memory array to be either protected or unprotected all at once. this reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. to take code and data protection to the next level, the at25dq321a incorporates a sector lockdown mechanism that allows any combination of individual 64-kbyte sectors to be locked down and become permanently read-only. this addresses the need of certain secure applications that require portions of the flash memory array to be permanently protected against malicious attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys, and routines. the device also contains a specialized otp (one-time programmable) security register that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. specifically designed for use in 3-volt systems, the at25dq321a supports read, program, and erase operations with a supply voltage range of 2.7v to 3.6v. no separate voltage is required for programming and erasing. 3 8718a?dflash?04/10 at25dq321a [preliminary] 2. pin descriptions and pinouts table 2-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in standby mode (not deep power-down mode), and the so pin will be in a high- impedance state. when the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin or i/o pins is always latched in on the rising edge of sck, while output data on the so pin or i/o pins is always clocked out on the falling edge of sck. - input si (i/o 0 ) serial input (i/o 0 ): the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched in on the rising edge of sck. with the dual-input and quad-input byte/page program commands, the si pin is used as an input pin (i/o 0 ) in conjunction with other pins to allow two bits (on i/o 1-0 ) or four bits (on i/o 3-0 ) of data to be clocked in on every rising edge of sck. with the dual-output and quad-output read array commands, the si pin becomes an output pin (i/o 0 ) and, along with other pins, allows two bits (on i/o 1- 0 ) or four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. to maintain consistency with spi nomenclature, the si (i/o 0 ) pin will be referenced as si throughout the document with exception to sections dealing with the dual-input and quad-input byte/page program commands as well as the dual-output and quad-output read array commands in which it will be referenced as i/o 0 . data present on the si pin will be ignored whenever the device is deselected ( cs is deasserted). - input/output so (i/o 1 ) serial output (i/o 1 ): the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. with the dual-input and quad-input byte/page program commands, the so pin becomes an input pin (i/o 1 ) and, along with other pins, allows two bits (on i/o 1-0 ) or four bits (on i/o 3-0 ) of data to be clocked in on every rising edge of sck. with the dual-output and quad-output read array commands, the so pin is used as an output pin (i/o 1 ) in conjunction with other pins to allow two bits (on i/o 1-0 ) or four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. to maintain consistency with spi nomenclature, the so (i/o 1 ) pin will be referenced as so throughout the document with exception to sections dealing with the dual-input and quad-input byte/page program commands as well as the dual-output and quad-output read array commands in which it will be referenced as i/o 1 . the so pin will be in a high-impedance state whenever the device is deselected ( cs is deasserted). - input/output 4 8718a?dflash?04/10 at25dq321a [preliminary] figure 2-1. pin configurations wp (i/o 2 ) write protect (i/o 2 ): the wp# pin controls the hardware locking feature of the device. see ?protection commands and features? on page 23. for more details on protection features and the wp pin. with the quad-input byte/page program command, the wp pin becomes an input pin (i/o 2 ) and, along with other pins, allows four bits (on i/o 3-0 ) of data to be clocked in on every rising edge of sck. with the quad-output read array command, the wp pin becomes an output pin (i/o 2 ) and, when used with other pins, allows four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. the qe bit in the configuration register must be set in order for the wp pin to be used as an i/o data pin. the wp pin must be driven at all times or pulled-high using an external pull-up resistor. low input/output hold (i/o 3 ) hold (i/o 3 ): the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses serial communication only and does not have an affect on internally self-timed operations such as a program or erase cycle. see ?hold? on page 49. for additional details on the hold operation. with the quad-input byte/page program command, the hold pin becomes an input pin (i/o 3 ) and, along with other pins, allows four bits (on i/o 3-0 ) of data to be clocked in on every rising edge of sck. with the quad-output read array command, the hold pin becomes an output pin (i/o 3 ) and, when used with other pins, allows four bits (on i/o 3-0 ) of data to be clocked out on every falling edge of sck. the qe bit in the configuration register must be set in order for the hold pin to be used as an i/o data pin. the hold pin must be driven at all times or pulled-high using an external pull- up resistor. low input/output v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. -power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. -power table 2-1. pin descriptions (continued) symbol name and function asserted state type 4 3 2 1 5 6 7 8 8-udfn 1 2 3 4 8 7 6 5 8-soic cs so (i/o 1 ) wp (i/o 2 ) gnd cs so (i/o 1 ) wp (i/o 2 ) gnd v cc hold (i/o 3 ) sck si (i/o 0 ) 16-soic v cc hold (i/o 3 ) sck si (i/o 0 ) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc v cc nc nc nc nc cs so sck si nc nc nc nc gnd wp 5 8718a?dflash?04/10 at25dq321a [preliminary] 3. block diagram figure 3-1. block diagram 4. memory array to provide the greatest flexibility, the memory array of the at25dq321a can be erased in four levels of granularity including a full chip erase. in addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. the size of the physical sectors is optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. the memory architecture diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. flash memory array y-gating cs sck note: i/o 3-0 pin naming convention is used for dual-i/o and quad-i/o commands so (i/o 1 ) si (i/o 0 ) y-decoder address latch x-decoder i/o buffers and latches control and protection logic sram data buffer wp (i/o 2 ) interface control and logic hold (i/o 3 ) 6 8718a?dflash?04/10 at25dq321a [preliminary] figure 4-1. memory architecture diagram 4kb 3fffffh ? 3ff000h 256 bytes 3fffffh ? 3fff00h 4kb 3fefffh ? 3fe000h 256 bytes 3ffeffh ? 3ffe00h 4kb 3fdfffh ? 3fd000h 256 bytes 3ffdffh ? 3ffd00h 4kb 3fcfffh ? 3fc000h 256 bytes 3ffcffh ? 3ffc00h 4kb 3fbfffh ? 3fb000h 256 bytes 3ffbffh ? 3ffb00h 4kb 3fafffh ? 3fa000h 256 bytes 3ffaffh ? 3ffa00h 4kb 3f9fffh ? 3f9000h 256 bytes 3ff9ffh ? 3ff900h 4kb 3f8fffh ? 3f8000h 256 bytes 3ff8ffh ? 3ff800h 4kb 3f7fffh ? 3f7000h 256 bytes 3ff7ffh ? 3ff700h 4kb 3f6fffh ? 3f6000h 256 bytes 3ff6ffh ? 3ff600h 4kb 3f5fffh ? 3f5000h 256 bytes 3ff5ffh ? 3ff500h 4kb 3f4fffh ? 3f4000h 256 bytes 3ff4ffh ? 3ff400h 4kb 3f3fffh ? 3f3000h 256 bytes 3ff3ffh ? 3ff300h 4kb 3f2fffh ? 3f2000h 256 bytes 3ff2ffh ? 3ff200h 4kb 3f1fffh ? 3f1000h 256 bytes 3ff1ffh ? 3ff100h 4kb 3f0fffh ? 3f0000h 256 bytes 3ff0ffh ? 3ff000h 4kb 3effffh ? 3ef000h 256 bytes 3fefffh ? 3fef00h 4kb 3eefffh ? 3ee000h 256 bytes 3feeffh ? 3fee00h 4kb 3edfffh ? 3ed000h 256 bytes 3fedffh ? 3fed00h 4kb 3ecfffh ? 3ec000h 256 bytes 3fecffh ? 3fec00h 4kb 3ebfffh ? 3eb000h 256 bytes 3febffh ? 3feb00h 4kb 3eafffh ? 3ea000h 256 bytes 3feaffh ? 3fea00h 4kb 3e9fffh ? 3e9000h 256 bytes 3fe9ffh ? 3fe900h 4kb 3e8fffh ? 3e8000h 256 bytes 3fe8ffh ? 3fe800h 4kb 3e7fffh ? 3e7000h 4kb 3e6fffh ? 3e6000h 4kb 3e5fffh ? 3e5000h 4kb 3e4fffh ? 3e4000h 256 bytes 0017ffh ? 001700h 4kb 3e3fffh ? 3e3000h 256 bytes 0016ffh ? 001600h 4kb 3e2fffh ? 3e2000h 256 bytes 0015ffh ? 001500h 4kb 3e1fffh ? 3e1000h 256 bytes 0014ffh ? 001400h 4kb 3e0fffh ? 3e0000h 256 bytes 0013ffh ? 001300h 256 bytes 0012ffh ? 001200h 256 bytes 0011ffh ? 001100h 256 bytes 0010ffh ? 001000h 4kb 00ffffh ? 00f000h 256 bytes 000fffh ? 000f00h 4kb 00efffh ? 00e000h 256 bytes 000effh ? 000e00h 4kb 00dfffh ? 00d000h 256 bytes 000dffh ? 000d00h 4kb 00cfffh ? 00c000h 256 bytes 000cffh ? 000c00h 4kb 00bfffh ? 00b000h 256 bytes 000bffh ? 000b00h 4kb 00afffh ? 00a000h 256 bytes 000affh ? 000a00h 4kb 009fffh ? 009000h 256 bytes 0009ffh ? 000900h 4kb 008fffh ? 008000h 256 bytes 0008ffh ? 000800h 4kb 007fffh ? 007000h 256 bytes 0007ffh ? 000700h 4kb 006fffh ? 006000h 256 bytes 0006ffh ? 000600h 4kb 005fffh ? 005000h 256 bytes 0005ffh ? 000500h 4kb 004fffh ? 004000h 256 bytes 0004ffh ? 000400h 4kb 003fffh ? 003000h 256 bytes 0003ffh ? 000300h 4kb 002fffh ? 002000h 256 bytes 0002ffh ? 000200h 4kb 001fffh ? 001000h 256 bytes 0001ffh ? 000100h 4kb 000fffh ? 000000h 256 bytes 0000ffh ? 000000h 64kb (sector 62) 64kb ? ? ? 64kb 32kb 32kb ? ? ? ? ? ? ? ? ? 64kb 64kb (sector 63) 32kb 32kb 64kb (sector 0) 32kb 32kb ? ? ? internal sectoring for 64kb 32kb 4kb 1-256 byte sector protection block erase block erase block erase page program function (d8h command) (52h command) (20h command) (02h command) block erase detail page program detail page address block address range range 7 8718a?dflash?04/10 at25dq321a [preliminary] 5. device operation the at25dq321a is controlled by a set of instructions that are sent from a host controller, commonly referred to as the spi master. the spi master communicates with the at25dq321a via the spi bus which is comprised of four signal lines: chip select ( cs), serial clock (sck), serial input (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the at25dq321a supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 5-1. spi mode 0 and 3 5.1 dual-i/o and quad-i/o operation the at25dq321a features a dual-input program mode and a dual-output read mode that allows two bits of data to be clocked into or out of the device every clock cycle to improve throughputs. to accomplish this, both the si and so pins are utilized as inputs/outputs for the transfer of data bytes. with the dual-input byte/page program command, the the so pin becomes an input along with the si pin. alternatively, with the dual-output read array command, the si pin becomes an output along with the so pin. for both dual-i/o commands, the so pin will be referred to as i/o 1 and the si pin will be referred to as i/o 0 . the device also supports a quad-input program mode and a quad-output read mode in which the w pand h o l d pins become data pins for even higher throughputs. for the quad-input byte/page program command and for the quad-output read array command, the h o l d, w p, so, and si pins are referred to as i/o 3-0 where h o l d becomes i/o 3 , w p becomes i/o 2 , so becomes i/o 1 , and si becomes i/o 0 . the qe bit in the configuration register must be set in order for both quad-i/o commands to be enabled and for the h o l d and w p pins to be converted to i/o data pins. so si sck cs 0 6 % / 6 % 0 6 % / 6 % 8 8718a?dflash?04/10 at25dq321a [preliminary] 6. commands and addressing a valid instruction or operation must always be started by first asserting the c s pin. after the c s pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. all opcode, address, and data bytes are transferred with the most-significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not supported by the at25dq321a will be ignored by the device and no operation will be started. the device will continue to ignore any data presented on the si pin until the start of the next operation ( c s pin being deasserted and then reasserted). in addition, if the c s pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of three bytes of information to be sent, representing address bits a23-a0. since the upper address limit of the at25dq321a memory array is 3fffffh, address bits a23-a22 are always ignored by the device. table 6-1. command listing command opcode clock frequency address bytes dummy bytes data bytes read commands read array 1bh 0001 1011 up to 100 mhz 3 2 1+ 0bh 0000 1011 up to 85 mhz 3 1 1+ 03h 0000 0011 up to 33 mhz 3 0 1+ dual-output read array 3bh 0011 1011 up to 70 mhz 3 1 1+ quad-output read array 6bh 0110 1011 up to 70 mhz 3 1 1+ program and erase commands block erase (4 kbytes) 20h 0010 0000 up to 100 mhz 3 0 0 block erase (32 kbytes) 52h 0101 0010 up to 100 mhz 3 0 0 block erase (64 kbytes) d8h 1101 1000 up to 100 mhz 3 0 0 chip erase 60h 0110 0000 up to 100 mhz 0 0 0 c7h 1100 0111 up to 100 mhz 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 up to 100 mhz 3 0 1+ dual-input byte/page program (1 to 256 bytes) a2h 1010 0010 up to 100 mhz 3 0 1+ quad-input byte/page program (1 to 256 bytes) 32h 0011 0010 up to 100 mhz 3 0 1+ program/erase suspend b0h 1011 0000 up to 100 mhz 0 0 0 program/erase resume d0h 1101 0000 up to 100 mhz 0 0 0 protection commands write enable 06h 0000 0110 up to 100 mhz 0 0 0 write disable 04h 0000 0100 up to 100 mhz 0 0 0 protect sector 36h 0011 0110 up to 100 mhz 3 0 0 unprotect sector 39h 0011 1001 up to 100 mhz 3 0 0 global protect/unprotect use write status register byte 1 command 9 8718a?dflash?04/10 at25dq321a [preliminary] 7. read commands 7.1 read array the read array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. the device incorporates an internal address counter that automatically increments on every clock cycle. three opcodes (1bh, 0bh, and 03h) can be used for the read array command. the use of each opcode depends on the maximum clock frequency that will be used to read data from the device. the 0bh opcode can be used at any clock frequency up to the maximum specified by f clk , and the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . the 1bh opcode allows the highest read performance possible and can be used at any clock frequency up to the maximum specified by f max ; however, use of the 1bh opcode at clock frequencies above f clk should be reserved to systems employing the rapids protocol. to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (1bh, 0bh, or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode is used for the read array operation. if the 1bh opcode is used, then two dummy bytes must be clocked into the device after the three address bytes. if the 0bh opcode is used, then a single dummy byte must be clocked in after the address bytes. read sector protection registers 3ch 0011 1100 up to 100 mhz 3 0 1+ security commands sector lockdown 33h 0011 0011 up to 100 mhz 3 0 1 freeze sector lockdown state 34h 0011 0100 up to 100 mhz 3 0 1 read sector lockdown registers 35h 0011 0101 up to 100 mhz 3 0 1+ program otp security register 9bh 1001 1011 up to 100 mhz 3 0 1+ read otp security register 77h 0111 0111 up to 100 mhz 3 2 1+ status and configuration register commands read status register 05h 0000 0101 up to 100 mhz 0 0 1+ write status register byte 1 01h 0000 0001 up to 100 mhz 0 0 1 write status register byte 2 31h 0011 0001 up to 100 mhz 0 0 1 read configuration register 3fh 0011 1111 up to 100 mhz 0 0 1+ write configuration register 3eh 0011 1110 up to 100 mhz 0 0 1 miscellaneous commands reset f0h 1111 0000 up to 100 mhz 0 0 1 read manufacturer and device id 9fh 1001 1111 up to 85 mhz 0 0 1 to 4 deep power-down b9h 1011 1001 up to 100 mhz 0 0 0 resume from deep power-down abh 1010 1011 up to 100 mhz 0 0 0 table 6-1. command listing (continued) command opcode clock frequency address bytes dummy bytes data bytes 10 8718a?dflash?04/10 at25dq321a [preliminary] after the three address bytes (and the dummy bytes or byte if using opcodes 1bh or 0bh) have been clocked in, additional clock cycles will result in data being output on the so pin. the data is always output with the msb of a byte first. when the last byte (3fffffh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-1. read array ? 1bh opcode figure 7-2. read array ? 0bh opcode figure 7-3. read array ? 03h opcode so si sck 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % ; ; ; ; ; ; ; ; 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' 2 1 7 & $ 5 ( 0 6 % ; ; ; ; ; ; ; ; ' 2 1 7 & $ 5 ( ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( cs so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % ; ; ; ; ; ; ; ; 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' 2 1 7 & $ 5 ( ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( so si sck 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( cs 11 8718a?dflash?04/10 at25dq321a [preliminary] 7.2 dual-output read array the dual-output read array command is similar to the standard read array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. unlike the standard read array command, however, the dual-output read array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one. the dual-output read array command can be used at any clock frequency up to the maximum specified by f rddo . to perform the dual-output read array operation, the c s pin must first be asserted and the opcode of 3bh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, a single dummy byte must also be clocked into the device. after the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being output on both the i/o 1 and i/o 0 pins. the data is always output with the msb of a byte first, and the msb is always output on the i/o 1 pin. during the first clock cycle, bit 7 of the first data byte will be output on the i/o 1 pin while bit 6 of the same data byte will be output on the i/o 0 pin. during the next clock cycle, bits 5 and 4 of the first data byte will be output on the i/o 1 and i/o 0 pins, respectively. the sequence continues with each byte of data being output after every four clock cycles. when the last byte (3fffffh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the c s pin will terminate the read operation and put the i/o 1-0 pins into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-4. dual-output read array 7.3 quad-output read array the quad-output read array command is similar to the dual-output read array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. unlike the dual-output read array command, however, the quad-output read array command allows four bits of data to be clocked out of the device on every clock cycle rather than two. the quad-output read array command can be used at any clock frequency up to the maximum specified by f rdqo . to perform the quad-output read array operation, the cs pin must first be asserted and the opcode of 6bh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, a single dummy byte must also be clocked into the device. so (i/o 1 ) si (i/o 0 ) sck 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % ; ; ; ; ; ; ; ; 0 6 % 0 6 % $ ' ' 5 ( 6 6 % , 7 6 $ $ ' 2 1 7 & $ 5 ( 2 8 7 3 8 7 ' $ 7 $ % < 7 ( 2 8 7 3 8 7 ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' cs 12 8718a?dflash?04/10 at25dq321a [preliminary] after the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being output on the i/o 3-0 pins. the data is always output with the msb of a byte first, and the msb is always output on the i/o 3 pin. during the first clock cycle, bit 7 of the first data byte will be output on the i/o 3 pin while bits 6, 5, and 4 of the same data byte will be output on the i/o 2 , i/o 1 , and i/o 0 pins, respectively. during the next clock cycle, bits 3, 2, 1, and 0 of the first data byte will be output on the i/o 3 , i/o 2 , i/o 1 , and i/o 0 pins, respectively. the sequence continues with each byte of data being output after every two clock cycles. when the last byte (3fffffh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the i/o 3-0 pins into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-5. quad-output read array 8. program and erase commands 8.1 byte/page program the byte/page program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. an erased memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 23 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte/page program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on an even 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the i/o 0 (si) sck 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % ; ; ; ; ; ; ; ; $ ' ' 5 ( 6 6 % , 7 6 $ $ ' 2 1 7 & $ 5 ( % < 7 ( 2 8 7 % < 7 ( 2 8 7 % < 7 ( 2 8 7 % < 7 ( 2 8 7 % < 7 ( 2 8 7 i/o 1 (so) + , * + , 0 3 ( ' $ 1 & ( ' ' ' ' ' ' ' ' ' ' i/o 2 (wp) + , * + , 0 3 ( ' $ 1 & ( ' ' ' ' ' ' ' ' ' ' i/o 3 (hold) 0 6 % 0 6 % 0 6 % 0 6 % 0 6 % + , * + , 0 3 ( ' $ 1 & ( ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' cs 13 8718a?dflash?04/10 at25dq321a [preliminary] beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the c s pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. in addition, if the address specified by a23-a0 points to a memory location within a sector that is in the protected state (see ?protect sector? on page 25 ) or locked down (see ?sector lockdown? on page 31 ), then the byte/page program command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the c s pin being deasserted on non-byte boundaries, or because the memory location to be programmed is protected or locked down. while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register. figure 8-1. byte program so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( $ $ $ $ $ $ $ $ $ 0 6 % ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ , 1 14 8718a?dflash?04/10 at25dq321a [preliminary] figure 8-2. page program 8.2 dual-input byte/page program the dual-input byte/page program command is similar to the standard byte/page program command and can be used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations. unlike the standard byte/page program command, however, the dual-input byte/page program command allows two bits of data to be clocked into the device on every clock cycle rather than just one. before the dual-input byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 23 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a dual-input byte/page program command, an opcode of a2h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device two bits at a time on both the i/o 1 and i/o 0 pins. the data is always input with the msb of a byte first, and the msb is always input on the i/o 1 pin. during the first clock cycle, bit 7 of the first data byte would be input on the i/o 1 pin while bit 6 of the same data byte would be input on the i/o 0 pin. during the next clock cycle, bits 5 and 4 of the first data byte would be input on the i/o 1 and i/o 0 pins, respectively. the sequence would continue with each byte of data being input after every four clock cycles. like the standard byte/page program command, all data clocked into the device is stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on an even 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the c s pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the so si sck 0 6 % 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( $ $ $ $ $ $ 0 6 % ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ , 1 % < 7 ( 0 6 % ' ' ' ' ' ' ' ' ' $ 7 $ , 1 % < 7 ( q cs 15 8718a?dflash?04/10 at25dq321a [preliminary] device will abort the operation and no data will be programmed into the memory array. in addition, if the address specified by a23-a0 points to a memory location within a sector that is in the protected state (see ?protect sector? on page 25 ) or locked down (see ?sector lockdown? on page 31 ), then the byte/page program command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the c s pin being deasserted on non-byte boundaries, or because the memory location to be programmed is protected or locked down. while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register. figure 8-3. dual-input byte program figure 8-4. dual-input page program sck 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ $ ' ' 5 ( 6 6 % , 7 6 $ $ 0 6 % ' ' ' ' ' ' ' ' , 1 3 8 7 ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( cs so (i/o 1 ) si (i/o 0 ) sck 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ , 1 3 8 7 ' $ 7 $ % < 7 ( 0 6 % ' ' ' ' ' ' ' ' , 1 3 8 7 ' $ 7 $ % < 7 ( q , 1 3 8 7 ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( cs so (i/o 1 ) si (i/o 0 ) 16 8718a?dflash?04/10 at25dq321a [preliminary] 8.3 quad-input byte/page program the quad-input byte/page program command is similar to the dual-input byte/page program command and can be used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations. unlike the dual-input byte/page program command, however, the quad-input byte/page program command allows four bits of data to be clocked into the device on every clock cycle rather than two. before the quad-input byte/page program command can be started, the write enable command must have been previously issued to the device ( see ?write enable? on page 23. ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a quad-input byte/page program command, an opcode of 32h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device four bits at a time on the i/o 3-0 pins. the data is always input with the msb of a byte first, and the msb is always input on the i/o 3 pin. during the first clock cycle, bit 7 of the first data byte would be input on the i/o 3 pin while bits 6, 5, and 4 of the same data byte would be input on the i/o 2 ,i/o 1 , and i/o 0 pins, respectively. during the next clock cycle, bits 3, 2, 1, and 0 of the first data byte would be input on the i/o 3 , i/o 2 , i/o 1 , and i/o 0 pins, respectively. the sequence would continue with each byte of data being input after every two clock cycles. like the standard byte/page program and dual-input byte/page program commands, all data clocked into the device is stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on a 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the c s pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the c s pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. in addition, if the address specified by a23-a0 points to a memory location within a sector that is in the protected state ( see ?protect sector? on page 25. ) or locked down ( see ?sector lockdown? on page 31. ), then the quad-input byte/page program command will not be executed, and the device will return to the idle state once the c s pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the c s pin being deasserted on non-byte boundaries, or because the memory location to be programmed is protected or locked down. while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. if a programming error arises, it will be indicated by the epe bit in the status register. 17 8718a?dflash?04/10 at25dq321a [preliminary] figure 8-5. quad-input byte program figure 8-6. quad-input page program i/o 0 (si) sck i/o 1 (so) i/o 2 (wp) i/o 3 (hold) cs msb msb 23 1 0 00110010 67 5 41011 9 812 33 31 32 29 30 opcode aaaa aaa aa address bits a23-a0 high-impedance high-impedance d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 msb high-impedance byte in i/o 0 (si) sck i/o 1 (so) i/o 2 (wp) i/o 3 (hold) cs msb msb 23 1 0 00110010 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode aaaa aaa aa d 5 d 4 d 1 d 0 address bits a23-a0 high-impedance d 6 d 2 high-impedance msb msb msb msb d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 d 5 d 4 d 1 d 0 d 6 d 2 d 7 d 3 msb high-impedance byte 1 in byte 2 in byte 3 in byte 4 in byte n in 18 8718a?dflash?04/10 at25dq321a [preliminary] 8.4 block erase a block of 4, 32, or 64 kbytes can be erased (all bits set to the logical ?1? state) in a single operation by using one of three different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is used for a 32-kbyte erase, and an opcode of d8h is used for a 64-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. to perform a block erase, the c s pin must first be asserted and the appropriate opcode (20h, 52h, or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the c s pin is deasserted, the device will erase the appropriate block. the erasing of the block is internally self-timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. therefore, for a 4-kbyte erase, address bits a11-a0 will be ignored by the device and their values can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14-a0 will be ignored, and for a 64-kbyte erase, address bits a15-a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the c spinis deasserted, and the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. if the address specified by a23-a0 points to a memory location within a sector that is in the protected or locked down state, then the block erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent, the c s pin being deasserted on non-byte boundaries, or because a memory location within the region to be erased is protected or locked down. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t blke time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an erase error occurs, it will be indicated by the epe bit in the status register. figure 8-7. block erase so si sck cs 0 6 % 0 6 % & & & & & & & & 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ $ $ $ $ ' ' 5 ( 6 6 % , 7 6 $ $ + , * + , 0 3 ( ' $ 1 & ( 19 8718a?dflash?04/10 at25dq321a [preliminary] 8.5 chip erase the entire memory array can be erased in a single operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. two opcodes, 60h and c7h, can be used for the chip erase command. there is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. to perform a chip erase, one of the two opcodes (60h or c7h) must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of the device is internally self- timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no erase will be performed. in addition, if any sector of the memory array is in the protected or locked down state, then the chip erase command will not be executed, and the device will return to the idle state once the c s pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the cs pin is deasserted on non-byte boundaries or if a sector is in the protected or locked down state. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t chpe time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. if an erase error occurs, it will be indicated by the epe bit in the status register. figure 8-8. chip erase so si sck cs 0 6 % & & & & & & & & 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 20 8718a?dflash?04/10 at25dq321a [preliminary] 8.6 program/erase suspend in some code plus data storage applications, it is often necessary to process certain high-level system interrupts that require relatively immediate reading of code or data from the flash memory. in such an instance, it may not be possible for the system to wait the microseconds or milliseconds required for the flash memory to complete a program or erase cycle. the program/erase suspend command allows a program or erase operation in progress to a particular 64-kbyte sector of the flash memory array to be suspended so that other device operations can be performed. for example, by suspending an erase operation to a particular sector, the system can perform functions such as a program or read operation within another 64-kbyte sector in the device. other device operations, such as a read status register, can also be performed while a program or erase operation is suspended. table 8-1 outlines the operations that are allowed and not allowed during a program or erase suspend. since the need to suspend a program or erase operation is immediate, the write enable command does not need to be issued prior to the program/erase suspend command being issued. therefore, the program/erase suspend command operates independently of the state of the wel bit in the status register. to perform a program/erase suspend, the c s pin must first be asserted and the opcode of b0h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the c s pin is deasserted, the program or erase operation currently in progress will be suspended within a time of t susp . the program suspend (ps) bit or the erase suspend (es) bit in the status register will then be set to the logical ?1? state to indicate that the program or erase operation has been suspended. in addition, the rdy/bsy bit in the status register will indicate that the device is ready for another operation. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on non-byte boundary (multiples of eight bits); otherwise, no suspend operation will be performed. if the program/erase suspend command is issued while the device is not busy performing a program or erase operation, (crdy/bsy is in the logic ?1? state), then the device is simply ignore the program/erase suspend command and the ps and es bits in the status register will indicate that the device is not in a suspend state, (ps and es will be a logic ?0?). read operations are not allowed to a 64-kbyte sector that has had its program or erase operation suspended. if a read is attempted to a suspended sector, then the device will output undefined data. therefore, when performing a read array operation to an unsuspended sector and the device?s internal address counter increments and crosses the sector boundary to a suspended sector, the device will then start outputting undefined data continuously until the address counter increments and crosses a sector boundary to an unsuspended sector. a program operation is not allowed to a sector that has been erase suspended. if a program operation is attempted to an erase suspended sector, then the program operation will abort and the wel bit in the status register will be reset back to the logical ?0? state. likewise, an erase operation is not allowed to a sector that has been program suspended. if attempted, the erase operation will abort and the wel bit in the status register will be reset to a logical ?0? state. during an erase suspend, a program operation to a different 64-kbyte sector can be started and subsequently suspended. this results in a simultaneous erase suspend/program suspend condition and will be indicated by the states of both the es and ps bits in the status register being set to the logical ?1? state. if a reset operation (see ?reset? on page 44 ) is performed while a sector is erase suspended, the suspend operation will abort and the contents of the block in the suspended sector will be left in an undefined state. however, if a reset is performed while a sector is program suspended, the suspend operation will abort but only the contents of the page that was being programmed and subsequently suspended will be undefined. the remaining pages in the 64-kbyte sector will retain their previous contents. 21 8718a?dflash?04/10 at25dq321a [preliminary] if an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a protect sector operation, then the device will simply ignore the opcode and no operation will be performed. the state of the wel bit in the status register, as well as the sprl (sector protection registers locked) and sle (sector lockdown enabled) bits, will not be affected. table 8-1. operations allowed and not allowed during a program or erase suspend. command operation during program suspend operation during erase suspend read commands read array (all opcodes) allowed allowed program and erase commands block erase not allowed not allowed chip erase not allowed not allowed byte/page program (all opcodes) not allowed allowed program/erase suspend not allowed allowed program/erase resume allowed allowed protection commands write enable not allowed allowed write disable not allowed allowed protect sector not allowed not allowed unprotect sector not allowed not allowed global protect/unprotect not allowed not allowed read sector protection registers allowed allowed security commands sector lockdown not allowed not allowed freeze sector lockdown state not allowed not allowed read sector lockdown registers allowed allowed program otp security register not allowed not allowed read otp security register allowed allowed status and configuration register commands read status register allowed allowed write status register (all opcodes) not allowed not allowed read configuration register allowed allowed write configuration register not allowed not allowed miscellaneous commands reset allowed allowed read manufacturer and device id allowed allowed deep power-down not allowed not allowed resume from deep power-down not allowed not allowed 22 8718a?dflash?04/10 at25dq321a [preliminary] figure 8-9. program/erase suspend 8.7 program/erase resume the program/erase resume command allows a suspended program or erase operation to be resumed and continue programming a flash page or erasing a flash memory block where it left off. as with the program/erase suspend command, the write enable command does not need to be issued prior to the program/erase resume command being issued. therefore, the program/erase resume command operates independently of the state of the wel bit in the status register. to perform a program/erase resume, the c s pin must first be asserted and the opcode of d0h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the c s pin is deasserted, the program or erase operation currently suspended will be resumed within a time of t res . the ps bit or the es bit in the status register will then be reset back to the logical ?0? state to indicate that the program or erase operation is no longer suspended. in addition, the rdy/bsy bit in the status register will indicate that the device is busy performing a program or erase operation. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no resume operation will be performed. during a simultaneous erase suspend/program suspend condition, issuing the program/erase resume command will result in the program operation resuming first. after the program operation has been completed, the program/erase resume command must be issued again in order for the erase operation to be resumed. while the device is busy resuming a program or erase operation, any attempts at issuing the program/erase suspend command will be ignored. therefore, if a resumed program or erase operation needs to be subsequently suspended again, the system must either wait the entire t res time before issuing the program/erase suspend command, or it must check the status of the rdy/bsy bit or the appropriate ps or es bit in the status register to determine if the previously suspended program or erase operation has resumed. figure 8-10. program/erase resume so si sck cs 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( so si sck cs 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 23 8718a?dflash?04/10 at25dq321a [preliminary] 9. protection commands and features 9.1 write enable the write enable command is used to set the write enable latch (wel) bit in the status register to a logical ?1? state. the wel bit must be set before a byte/page program, erase, protect sector, unprotect sector, sector lockdown, freeze sector lockdown state, program otp security register, write status register, or write configuration register command can be executed. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. if the wel bit in the status register is not set prior to the issuance of one of these commands, then the command will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the c s pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the complete opcode must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-1. write enable so si sck cs 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 24 8718a?dflash?04/10 at25dq321a [preliminary] 9.2 write disable the write disable command is used to reset the write enable latch (wel) bit in the status register to the logical "0" state. with the wel bit reset, all byte/page program, erase, protect sector, unprotect sector, sector lockdown, freeze sector lockdown state, program otp security register, write status register, and write configuration register commands will not be executed. other conditions can also cause the wel bit to be reset; for more details, refer to the wel bit section of the status register description. to issue the write disable command, the c s pin must first be asserted and the opcode of 04h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the c s pin is deasserted, the wel bit in the status register will be reset to a logical ?0?. the complete opcode must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-2. write disable so si sck cs 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 25 8718a?dflash?04/10 at25dq321a [preliminary] 9.3 protect sector every physical 64-kbyte sector of the device has a corresponding single-bit sector protection register that is used to control the software protection of a sector. upon device power-up, each sector protection register will default to the logical ?1? state indicating that all sectors are protected and cannot be programmed or erased. issuing the protect sector command to a particular sector address will set the corresponding sector protection register to the logical ?1? state. the following table outlines the two states of the sector protection registers. table 9-1. sector protection register values before the protect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the protect sector command, the c s pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be protected. any additional data clocked into the device will be ignored. when the c s pin is deasserted, the sector protection register corresponding to the physical sector addressed by a23-a0 will be set to the logical ?1? state, and the sector itself will then be protected from program and erase operations. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation. when the device aborts the protect sector operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous protecting or unprotecting of sectors, the sector protection registers can themselves be locked from updates by using the sprl (sector protection registers locked) bit of the status register (please refer to the status register description for more details). if the sector protection registers are locked, then any attempts to issue the protect sector command will be ignored, and the device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-3. protect sector value sector protection status 0 sector is unprotected and can be programmed and erased. 1 sector is protected and cannot be programmed or erased. this is the default state. so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ $ $ $ $ ' ' 5 ( 6 6 % , 7 6 $ $ + , * + , 0 3 ( ' $ 1 & ( 26 8718a?dflash?04/10 at25dq321a [preliminary] 9.4 unprotect sector issuing the unprotect sector command to a particular sector address will reset the corresponding sector protection register to the logical ?0? state (see table 9-1 for sector protection register values). every physical sector of the device has a corresponding single-bit sector protection register that is used to control the software protection of a sector. before the unprotect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the unprotect sector command, the c s pin must first be asserted and the opcode of 39h must be clocked into the device. after the opcode has been clocked in, the three address bytes designating any address within the sector to be unprotected must be clocked in. any additional data clocked into the device after the address bytes will be ignored. when the c s pin is deasserted, the sector protection register corresponding to the sector addressed by a23-a0 will be reset to the logical ?0? state, and the sector itself will be unprotected. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking or unlocking of sectors, the sector protection registers can themselves be locked from updates by using the sprl (sector protection registers locked) bit of the status register (please refer to the status register description for more details). if the sector protection registers are locked, then any attempts to issue the unprotect sector command will be ignored, and the device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the c s pin has been deasserted. figure 9-4. unprotect sector so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ $ $ $ $ ' ' 5 ( 6 6 % , 7 6 $ $ + , * + , 0 3 ( ' $ 1 & ( 27 8718a?dflash?04/10 at25dq321a [preliminary] 9.5 global protect/unprotect the global protect and global unprotect features can work in conjunction with the protect sector and unprotect sector functions. for example, a system can globally protect the entire memory array and then use the unprotect sector command to individually unprotect certain sectors and individually reprotect them later by using the protect sector command. likewise, a system can globally unprotect the entire memory array and then individually protect certain sectors as needed. performing a global protect or global unprotect is accomplished by writing a certain combination of data to the status register using the write status register byte 1 command (see ?write status register byte 1? on page 40 for command execution details). the write status register command is also used to modify the sprl (sector protection registers locked) bit to control hardware and software locking. to perform a global protect, the appropriate wp pin and sprl conditions must be met, and the system must write a logical ?1? to bits 5, 4, 3, and 2 of the first byte of the status register. conversely, to perform a global unprotect, the same wp and sprl conditions must be met but the system must write a logical ?0? to bits 5, 4, 3, and 2 of the first byte of the status register. table 9-2 details the conditions necessary for a global protect or global unprotect to be performed. sectors that have been erase or program suspended must remain in the unprotected state. if a global protect operation is attempted while a sector is erase or program suspended, the protection operation will abort, the protection states of all sectors in the flash memory array will not change, and wel bit in the status register will be reset back to a logical ?0?. 28 8718a?dflash?04/10 at25dq321a [preliminary] table 9-2. valid sprl and global protect/unprotect conditions essentially, if the sprl bit of the status register is in the logical ?0? state (sector protection registers are not locked), then writing a 00h to the first byte of the status register will perform a global unprotect without changing the state of the sprl bit. similarly, writing a 7fh to the first byte of the status register will perform a global protect and keep the sprl bit in the logical ?0? state. the sprl bit can, of course, be changed to a logical ?1? by writing an ffh if software-locking or hardware-locking is desired along with the global protect. if the desire is to only change the sprl bit without performing a global protect or global unprotect, then the system can simply write a 0fh to the first byte of the status register to change the sprl bit from a logical ?1? to a logical ?0? provided the wp pin is deasserted. likewise, the system can write an f0h to change the sprl bit from wp state current sprl value new write status register byte 1 data protection operation new sprl value bit 76543210 00 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1x0000xx 1x0001xx 1x1110xx 1x1111xx global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1 0 1 xxxxxxxx no change to the current protection level. all sectors currently protected will remain protected and all sectors currently unprotected will remain unprotected. the sector protection registers are hard-locked and cannot be changed when the wp pin is low and the current state of sprl is 1. therefore, a global protect/unprotect will not occur. in addition, the sprl bit cannot be changed (the wp pin must be high in order to change sprl back to a 0). 10 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1x0000xx 1x0001xx 1x1110xx 1x1111xx global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 global unprotect ? all sector protection registers reset to 0 no change to current protection. no change to current protection. no change to current protection. global protect ? all sector protection registers set to 1 0 0 0 0 0 1 1 1 1 1 11 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1x0000xx 1x0001xx 1x1110xx 1x1111xx no change to the current protection level. all sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected. the sector protection registers are soft-locked and cannot be changed when the current state of sprl is 1. therefore, a global protect/unprotect will not occur. however, the sprl bit can be changed back t o a 0 from a 1 since the wp pin is high. to perform a global protect/unprotect, the write status register command must be issued again after the sprl bit has been changed fro ma1toa0. 0 0 0 0 0 1 1 1 1 1 29 8718a?dflash?04/10 at25dq321a [preliminary] a logical ?0? to a logical ?1? without affecting the current sector protection status (no changes will be made to the sector protection registers). when writing to the first byte of the status register, bits 5, 4, 3, and 2 will not actually be modified but will be decoded by the device for the purposes of the global protect and global unprotect functions. only bit 7, the sprl bit, will actually be modified. therefore, when reading the first byte of the status register, bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of the wp pin and the sector protection status. please refer to ?read status register? on page 36 and table 11-1 on page 36 for details on the status register format and what values can be read for bits 5, 4, 3, and 2. 9.6 read sector protection registers the sector protection registers can be read to determine the current software protection status of each sector. reading the sector protection registers, however, will not determine the status of the wp pin. to read the sector protection register for a particular sector, the cs pin must first be asserted and the opcode of 3ch must be clocked in. once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. after the last address byte has been clocked in, the device will begin outputting data on the so pin during every subsequent clock cycle. the data being output will be a repeating byte of either ffh or 00h to denote the value of the appropriate sector protection register. at clock frequencies above f clk , the first byte of data output will not be valid. therefore, if operating at clock frequencies above f clk , at least two bytes of data must be clocked out from the device in order to determine the correct status of the appropriate sector protection register. table 9-3. read sector protection register - output data deasserting the cs pin will terminate the read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. in addition to reading the individual sector protection registers, the software protection status (swp) bits in the status register can be read to determine if all, some, or none of the sectors are software protected (refer to ?read status register? on page 36 for more details). figure 9-5. read sector protection register output data sector protection register value 00h sector protection register value is 0 (sector is unprotected). ffh sector protection register value is 1 (sector is protected). so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 30 8718a?dflash?04/10 at25dq321a [preliminary] 9.7 protected states and the write protect ( wp) pin the w p pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown status of the memory array. instead, the w p pin, in conjunction with the sprl (sector protection registers locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met-the w p pin must be asserted and the sprl bit must be in the logical ?1? state. when hardware locking is active, the sector protection registers are locked and the sprl bit itself is also locked. therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. these states cannot be changed as long as hardware locking is active, so the protect sector, unprotect sector, and write status register commands will be ignored. in order to modify the protection status of a sector, the wp pin must first be deasserted, and the sprl bit in the status register must be reset back to the logical ?0? state using the write status register command. when resetting the sprl bit back to a logical ?0?, it is not possible to perform a global protect or global unprotect at the same time since the sector protection registers remain soft-locked until after the write status register command has been executed. if the wp pin is permanently connected to gnd, then once the sprl bit is set to a logical ?1?, the only way to reset the bit back to the logical ?0? state is to power-cycle the device. this allows a system to power-up with all sectors software protected but not hardware locked. therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the sprl bit in the status register. when the w p pin is deasserted, or if the wp pin is permanently connected to v cc , the sprl bit in the status register can still be set to a logical ?1? to lock the sector protection registers. this provides a software locking ability to prevent erroneous protect sector or unprotect sector commands from being processed. when changing the sprl bit to a logical ?1? from a logical ?0?, it is also possible to perform a global protect or global unprotect at the same time by writing the appropriate values into bits 5, 4, 3, and 2 of the first byte of the status register. tables 9-4 and 9-5 detail the various protection and locking states of the device. note: 1. ?n? represents a sector number table 9-5. hardware and software locking table 9-4. sector protection register states wp sector protection register n (1) sector n (1) x (don't care) 0 unprotected 1 protected wp sprl locking sprl change allowed sector protection registers 00 can be modified from0to1 unlocked and modifiable using the protect and unprotect sector commands. global protect and unprotect can also be performed. 01 hardware locked locked locked in current state. protect and unprotect sector commands will be ignored. global protect and unprotect cannot be performed. 10 can be modified from0to1 unlocked and modifiable using the protect and unprotect sector commands. global protect and unprotect can also be performed. 11 software locked can be modified from1to0 locked in current state. protect and unprotect sector commands will be ignored. global protect and unprotect cannot be performed. 31 8718a?dflash?04/10 at25dq321a [preliminary] 10. security commands 10.1 sector lockdown certain applications require that portions of the flash memory array be permanently protected against malicious attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys, and routines. to address these applications, the device incorporates a sector lockdown mechanism that allows any combination of individual 64-kbyte sectors to be permanently locked so that they become read only. once a sector is locked down, it can never be erased or programmed again, and it can never be unlocked from the locked down state. each 64-kbyte physical sector has a corresponding single-bit sector lockdown register that is used to control the lockdown status of that sector. these registers are nonvolatile and will retain their state even after a device power- cycle or reset operation. the following table outlines the two states of the sector lockdown registers. table 10-1. sector lockdown register values issuing the sector lockdown command to a particular sector address will set the corresponding sector lockdown register to the logical ?1? state. each sector lockdown register can only be set once; therefore, once set to the logical ?1? state, a sector lockdown register cannot be reset back to the logical ?0? state. before the sector lockdown command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. in addition, the sector lockdown enabled (sle) bit in the status register must have also been previously set to the logical ?1? state by using the write status register byte 2 command (see ?write status register byte 2? on page 41 ). to issue the sector lockdown command, the c s pin must first be asserted and the opcode of 33h must be clocked into the device followed by three address bytes designating any address within the 64-kbyte sector to be locked down. after the three address bytes have been clocked in, a confirmation byte of d0h must also be clocked in immediately following the three address bytes. any additional data clocked into the device after the first byte of data will be ignored. when the c s pin is deasserted, the sector lockdown register corresponding to the sector addressed by a23-a0 will be set to the logical ?1? state, and the sector itself will then be permanently locked down from program and erase operations within a time of t lock . in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes and the correct confirmation byte value of d0h must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation. when the device aborts the sector lockdown operation, the state of the corresponding sector lockdown register as well as the sle bit in the status register will be unchanged; however, the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking down of sectors, the sector lockdown command can be enabled and disabled as needed by using the sle bit in the status register. in addition, the current sector lockdown state can be frozen so that no further modifications to the sector lockdown registers can be made (see ?freeze sector lockdown state? below). if the sector lockdown command is disabled or if the sector lockdown state is frozen, then any attempts to issue the sector lockdown command will be ignored, and the device will reset the wel bit in the status register back to a logical ?0? and return to the idle state once the c s pin has been deasserted. value sector lockdown status 0 sector is not locked down and can be programmed and erased. this is the default state. 1 sector is permanently locked down and can never be programmed or erased again. 32 8718a?dflash?04/10 at25dq321a [preliminary] figure 10-1. sector lockdown 10.2 freeze sector lockdown state the current sector lockdown state can be permanently frozen so that no further modifications to the sector lockdown registers can be made; therefore, the sector lockdown command will be permanently disabled, and no additional sectors can be locked down aside from those already locked down. any attempts to issue the sector lockdown command after the sector lockdown state has been frozen will be ignored. before the freeze sector lockdown state command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. in addition, the sector lockdown enabled (sle) bit in the status register must have also been previously set to the logical ?1? state. to issue the freeze sector lockdown state command, the c s pin must first be asserted and the opcode of 34h must be clocked into the device followed by three command specific address bytes of 55aa40h. after the three address bytes have been clocked in, a confirmation byte of d0h must be clocked in immediately following the three address bytes. any additional data clocked into the device will be ignored. when the c s pin is deasserted, the current sector lockdown state will be permanently frozen within a time of t lock . in addition, the wel bit in the status register will be reset back to the logical ?0? state, and the sle bit will be permanently reset to a logical ?0? to indicate that the sector lockdown command is permanently disabled. the complete and correct three address bytes and the confirmation byte must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation. when the device aborts the freeze sector lockdown state operation, the wel bit in the status register will be reset to a logical ?0?; however, the state of the sle bit will be unchanged. figure 10-2. freeze sector lockdown state so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( $ $ $ $ $ $ 0 6 % $ ' ' 5 ( 6 6 % , 7 6 $ $ & 2 1 ) , 5 0 $ 7 , 2 1 % < 7 ( , 1 so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 0 6 % $ ' ' 5 ( 6 6 % , 7 6 $ $ & 2 1 ) , 5 0 $ 7 , 2 1 % < 7 ( , 1 33 8718a?dflash?04/10 at25dq321a [preliminary] 10.3 read sector lockdown registers the sector lockdown registers can be read to determine the current lockdown status of each physical 64-kbyte sector. to read the sector lockdown register for a particular 64-kbyte sector, the c s pin must first be asserted and the opcode of 35h must be clocked in. once the opcode has been clocked in, three address bytes designating any address within the 64-kbyte sector must be clocked in. after the address bytes have been clocked in, data will be output on the so pin during every subsequent clock cycle. the data being output will be a repeating byte of either ffh or 00h to denote the value of the appropriate sector lockdown register. at clock frequencies above f clk , the first byte of data output will not be valid. therefore, if operating at clock frequencies above f clk , at least two bytes of data must be clocked out from the device in order to determine the correct status of the appropriate sector lockdown register. table 10-2. read sector lockdown register - output data deasserting the cs pin will terminate the read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 10-3. read sector lockdown register 10.4 program otp security register the device contains a specialized otp (one-time programmable) security register that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. the otp security register is independent of the main flash memory array and is comprised of a total of 128 bytes of memory divided into two portions. the first 64 bytes (byte locations 0 through 63) of the otp security register are allocated as a one-time user-programmable space. once these 64 bytes have been programmed, they cannot be erased or reprogrammed. the remaining 64 bytes of the otp security register (byte locations 64 through 127) are factory programmed by atmel and will contain a unique value for each device. the factory programmed data is fixed and cannot be changed. output data sector lockdown register value 00h sector lockdown register value is 0 (sector is not locked down). ffh sector lockdown register value is 1 (sector is permanently locked down). so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % ; ; ; ; ; ; ; ; 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' 2 1 7 & $ 5 ( ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 34 8718a?dflash?04/10 at25dq321a [preliminary] table 10-3. otp security register the user-programmable portion of the otp security register does not need to be erased before it is programmed. in addition, the program otp security register command operates on the entire 64-byte user-programmable portion of the otp security register at one time. once the user-programmable space has been programmed with any number of bytes, the user-programmable space cannot be programmed again; therefore, it is not possible to only program the first two bytes of the register and then program the remaining 62 bytes at a later time. before the program otp security register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to program the otp security register, the c s pin must first be asserted and an opcode of 9bh must be clocked into the device followed by the three address bytes denoting the first byte location of the otp security register to begin programming at. since the size of the user-programmable portion of the otp security register is 64 bytes, the upper order address bits do not need to be decoded by the device. therefore, address bits a23-a6 will be ignored by the device and their values can be either a logical ?1? or ?0?. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in the internal buffer. if the starting memory address denoted by a23-a0 does not start at the beginning of the otp security register memory space (a5-a0 are not all 0), then special circumstances regarding which otp security register locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the 64-byte user-programmable space will wrap around back to the beginning of the otp security register. for example, if the starting address denoted by a23-a0 is 00003eh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at otp security register addresses 00003eh and 00003fh while the last byte of data will be programmed at address 000000h. the remaining bytes in the otp security register (addresses 000001h through 00003dh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 64 bytes of data are sent to the device, then only the last 64 bytes sent will be latched into the internal buffer. when the c s pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate otp security register locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 64 bytes of data were sent to the device, then the remaining bytes within the otp security register will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t otpp . it is not possible to suspend the programming of the otp security register. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the c s pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and the user-programmable portion of the otp security register will not be programmed. the wel bit in the status register will be reset back to the logical ?0? state if the otp security register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on non-byte boundaries, or because the user-programmable portion of the otp security register was previously programmed. while the device is programming the otp security register, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t otpp time to determine if the data bytes have finished programming. at some point before the otp security register programming completes, the wel bit in the status register will be reset back to the logical ?0? state. security register byte number 01 ... 62 63 64 65 ... 126 127 one-time user programmable factory programmed by atmel 35 8718a?dflash?04/10 at25dq321a [preliminary] if the device is powered-down during the otp security register program cycle, then the contents of the 64-byte user programmable portion of the otp security register cannot be guaranteed and cannot be programmed again. the program otp security register command utilizes the internal 256-buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. figure 10-4. program otp security register 10.5 read otp security register the otp security register can be sequentially read in a similar fashion to the read array operation up to the maximum clock frequency specified by f max . to read the otp security register, the cs pin must first be asserted and the opcode of 77h must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the otp security register. following the three address bytes, two dummy bytes must be clocked into the device before data can be output. after the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in otp security register data being output on the so pin. when the last byte (00007fh) of the otp security register has been read, the device will continue reading back at the beginning of the register (000000h). no delays will be incurred when wrapping around from the end of the register to the beginning of the register. deasserting the cs pin will terminate the read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 10-5. read otp security register so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( $ $ $ $ $ $ 0 6 % ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ , 1 % < 7 ( 0 6 % ' ' ' ' ' ' ' ' ' $ 7 $ , 1 % < 7 ( q so si sck cs 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ ; ; ; 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ 0 6 % ; ; ; ; ; ; ' 2 1 7 & $ 5 ( ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 36 8718a?dflash?04/10 at25dq321a [preliminary] 11. status register commands 11.1 read status register the two-byte status register can be read to determine the device?s ready/busy status, as well as the status of many other functions such as hardware locking and software protection. the status register can be read at any time, including during an internally self-timed program or erase operation. to read the status register, the c s pin must first be asserted and the opcode of 05h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the second byte of the status register has been clocked out, the sequence will repeat itself starting again with the first byte of the status register as long as the c s pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence will output new data. the rdy/bsy status is available for both bytes of the status register and is updated for each byte. at clock frequencies above f clk , the first two bytes of data output from the status register will not be valid. therefore, if operating at clock frequencies above f clk , at least four bytes of data must be clocked out from the device in order to read the correct values of both bytes of the status register. deasserting the c s pin will terminate the read status register operation and put the so pin into a high- impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. notes: 1. only bit 7 of status register byte 1 will be modified when using the write status register byte 1 command. 2. r/w = readable and writeable r = readable only table 11-1. status register format ? byte 1 bit (1) name type (2) description 7 sprl sector protection registers locked r/w 0 sector protection registers are unlocked (default). 1 sector protection registers are locked. 6 res reserved for future use r 0 reserved for future use. 5 epe erase/program error r 0 erase or program operation was successful. 1 erase or program error detected. 4 wpp write protect ( wp) pin status r 0 wp is asserted. 1 wp is deasserted. 3:2 swp software protection status r 00 all sectors are software unprotected (all sector protection registers are 0). 01 some sectors are software protected. read individual sector protection registers to determine which sectors are protected. 10 reserved for future use. 11 all sectors are software protected (all sector protection registers ar e 1 ? default). 1 wel write enable latch status r 0 device is not write enabled (default). 1 device is write enabled. 0 rdy/bsy ready/busy status r 0 device is ready. 1 device is busy with an internal operation. 37 8718a?dflash?04/10 at25dq321a [preliminary] notes: 1. only bits 4 and 3 of status register byte 2 will be modified when using the write status register byte 2 command. 2. r/w = readable and writeable r = readable only 11.1.1 sprl bit the sprl bit is used to control whether the sector protection registers can be modified or not. when the sprl bit is in the logical ?1? state, all sector protection registers are locked and cannot be modified with the protect sector and unprotect sector commands (the device will ignore these commands). in addition, the global protect and global unprotect features cannot be performed. any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected. when the sprl bit is in the logical ?0? state, all sector protection registers are unlocked and can be modified (the protect sector and unprotect sector commands, as well as the global protect and global unprotect features, will be processed as normal). the sprl bit defaults to the logical ?0? state after device power-up. the reset command has no effect on the sprl bit. the sprl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is asserted, then the sprl bit may only be changed from a logical ?0? (sector protection registers are unlocked) to a logical ?1? (sector protection registers are locked). in order to reset the sprl bit back to a logical ?0? using the write status register byte 1 command, the wp pin will have to first be deasserted. the sprl bit is the only bit of status register byte 1 that can be user modified via the write status register byte 1 command. table 11-2. status register format ? byte 2 bit (2) name type (2) description 7 res reserved for future use r 0 reserved for future use. 6 res reserved for future use r 0 reserved for future use. 5 res reserved for future use r 0 reserved for future use. 4 rste reset enabled r/w 0 reset command is disabled (default). 1 reset command is enabled. 3 sle sector lockdown enabled r/w 0 sector lockdown and freeze sector lockdown state commands are disabled (default). 1 sector lockdown and freeze sector lockdown state commands are enabled. 2 ps program suspend status r 0 no sectors are program suspended (default). 1 a sector is program suspended. 1 es erase suspend status r 0 no sectors are erase suspended (default). 1 a sector is erase suspended. 0 rdy/bsy ready/busy status r 0 device is ready. 1 device is busy with an internal operation. 38 8718a?dflash?04/10 at25dq321a [preliminary] 11.1.2 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logical ?1? state. the epe bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or program a protected region or a locked down sector, an attempt to erase or program a suspended sector, or if the wel bit is not set prior to an erase or program operation. the epe bit will be updated after every erase and program operation. 11.1.3 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 11.1.4 swp bits the swp bits provide feedback on the software protection status for the device. there are three possible combinations of the swp bits that indicate whether none, some, or all of the sectors have been protected using the protect sector command or the global protect feature. if the swp bits indicate that some of the sectors have been protected, then the individual sector protection registers can be read with the read sector protection registers command to determine which sectors are in fact protected. 11.1.5 wel bit the wel bit indicates the current status of the internal write enable latch. when the wel bit is in the logical ?0? state, the device will not accept any byte/page program, erase, protect sector, unprotect sector, sector lockdown, freeze sector lockdown state, program otp security register, write status register, or write configuration register commands. the wel bit defaults to the logical ?0? state after a device power-up or reset operation. in addition, the wel bit will be reset to the logical ?0? state automatically under the following conditions: ? write disable operation completes successfully ? write status register operation completes successfully or aborts ? write configuration register operation completes successfully or aborts ? protect sector operation completes successfully or aborts ? unprotect sector operation completes successfully or aborts ? sector lockdown operation completes successfully or aborts ? freeze sector lockdown state operation completes successfully or aborts ? program otp security register operation completes successfully or aborts ? byte/page program operation completes successfully or aborts ? block erase operation completes successfully or aborts ? chip erase operation completes successfully or aborts ? hold condition aborts if the wel bit is in the logical ?1? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode for a byte/page program, erase, protect sector, unprotect sector, sector lockdown, freeze sector lockdown state, program otp security register, write status register, or write configuration register command must have been clocked into the device. 39 8718a?dflash?04/10 at25dq321a [preliminary] 11.1.6 rste bit the rste bit is used to enable or disable the reset command. when the rste bit is in the logical ?0? state (the default state after power-up), the reset command is disabled and any attempts to reset the device using the reset command will be ignored. when the rste bit is in the logical ?1? state, the reset command is enabled. the rste bit will retain its state as long as power is applied to the device. once set to the logical ?1? state, the rste bit will remain in that state until it is modified using the write status register byte 2 command or until the device has been power cycled. the reset command itself will not change the state of the rste bit. 11.1.7 sle bit the sle bit is used to enable and disable the sector lockdown and freeze sector lockdown state commands. when the sle bit is in the logical ?0? state (the default state after power-up), the sector lockdown and freeze sector lockdown commands are disabled. if the sector lockdown and freeze sector lockdown commands are disabled, then any attempts to issue the commands will be ignored. this provides a safeguard for these commands against accidental or erroneous execution. when the sle bit is in the logical ?1? state, the sector lockdown and freeze sector lockdown state commands are enabled. unlike the wel bit, the sle bit does not automatically reset after certain device operations. therefore, once set, the sle bit will remain in the logical ?1? state until it is modified using the write status register byte 2 command or until the device has been power cycled. the reset command has no effect on the sle bit. if the freeze sector lockdown state command has been issued, then the sle bit will be permanently reset in the logical ?0? state to indicate that the sector lockdown command has been disabled. 11.1.8 ps bit the ps bit indicates whether or not a sector is in the program suspend state. 11.1.9 es bit the es bit indicates whether or not a sector is in the erase suspend state. 11.1.10 rdy/bsy bit the rdy/bsy bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. to poll the rdy/bsy bit to detect the completion of a program or erase cycle, new status register data must be continually clocked out of the device until the state of the rdy/bsy bit changes from a logical ?1? to a logical ?0?. figure 11-1. read status register so si sck cs 0 6 % 2 3 & 2 ' ( 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' 0 6 % ' ' ' ' ' ' ' ' ' ' ' ' ' ' 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 % < 7 ( 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 % < 7 ( 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 40 8718a?dflash?04/10 at25dq321a [preliminary] 11.2 write status register byte 1 the write status register byte 1 command is used to modify the sprl bit of the status register and/or to perform a global protect or global unprotect operation. before the write status register byte 1 command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register byte 1 command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. the one byte of data consists of the sprl bit value, a don?t care bit, four data bits to denote whether a global protect or unprotect should be performed, and two additional don?t care bits (see table 11-3 ). any additional data bytes that are sent to the device will be ignored. when the cs pin is deasserted, the sprl bit in the status register will be modified, and the wel bit in the status register will be reset back to a logical ?0?. the values of bits 5, 4, 3, and 2 and the state of the sprl bit before the write status register byte 1 command was executed (the prior state of the sprl bit) will determine whether or not a global protect or global unprotect will be performed. please refer to ?global protect/unprotect? on page 27 for more details. the complete one byte of data must be clocked into the device before the c s pin is deasserted, and the c spin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the sprl bit will not change, no potential global protect or unprotect will be performed, and the wel bit in the status register will be reset back to the logical ?0? state. if the wp pin is asserted, then the sprl bit can only be set to a logical ?1?. if an attempt is made to reset the sprl bit to a logical ?0? while the wp pin is asserted, then the write status register byte 1 command will be ignored, and the wel bit in the status register will be reset back to the logical ?0? state. in order to reset the sprl bit to a logical ?0?, the wp pin must be deasserted. table 11-3. write status register byte 1 format figure 11-2. write status register byte 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sprl x global protect/unprotect x x so si sck cs 0 6 % 2 3 & 2 ' ( 0 6 % ' ; ' ' ' ' ; ; 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 , 1 % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 41 8718a?dflash?04/10 at25dq321a [preliminary] 11.3 write status register byte 2 the write status register byte 2 command is used to modify the rste and sle bits of the status register. using the write status register byte 2 command is the only way to modify the rste and sle bits in the status register during normal device operation, and the sle bit can only be modified if the sector lockdown state has not been frozen. before the write status register byte 2 command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register byte 2 command, the cs pin must first be asserted and the opcode of 31h must be clocked into the device followed by one byte of data. the one byte of data consists of three don?t care bits, the rste bit value, the sle bit value, and three additional don?t care bits (see table 11-4 ). any additional data bytes that are sent to the device will be ignored. when the c s pin is deasserted, the rste and sle bits in the status register will be modified, and the wel bit in the status register will be reset back to a logical ?0?. the sle bit will only be modified if the freeze sector lockdown state command has not been previously issued. the complete one byte of data must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the rste and sle bits will not change, and the wel bit in the status register will be reset back to the logical ?0? state. table 11-4. write status register byte 2 format figure 11-3. write status register byte 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x rste sle x x x so si sck cs 0 6 % 2 3 & 2 ' ( 0 6 % ; ; ; ' ' ; ; ; 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 , 1 % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 42 8718a?dflash?04/10 at25dq321a [preliminary] 11.4 read configuration register the non-volatile configuration register can be read to determine if the quad-input byte/page program and quad- output read array commands have been enabled. unlike the status register, the configuration register can only be read when the device is in an idle state (when the rdy/bsy bit of the status register indicates that the device is in a ready state). to read the configuration register, the cs pin must first be asserted and the opcode of 3fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the one byte of configuration register data on the so pin during subsequent clock cycles. the data being output will be a repeating byte as long as the cs pin remains asserted and the clock pin is being pulsed. at clock frequencies above f clk , the first byte of data output will not be valid. therefore, if operating at clock frequencies above f clk , at least two bytes of data must be clocked out from the device in order to determine the correct value of the configuration register. deasserting the c s pin will terminate the read configuration register operation and put the so pin into a high- impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. the configuration register is a non-volatile register; therefore, the contents of the configuration register are not affected by power cycles or power-on reset operations. table 11-5. configuration register format notes: 1. only bit 7 of the configuration register will be modified when using the write configuration register command. 2. r/w = readable and writeable r = readable only 11.4.1 qe bit the qe bit is used to control whether the quad-input byte/page program and quad-output read array commands are enabled or disabled. when the qe bit is in the logical ?1? state, the quad-input byte/page program and quad-output read array commands are enabled and will be recognized by the device. in addition, the w p and h o l d functions are disabled, and the w p and h o l d pins themselves operate as a bidirectional input/output pins ( wp is i/o 2 and hold is i/o 3 ). when the qe bit is in the logical ?0? state, the quad-input byte/page program and quad-output read array commands are disabled and will not be recognized by the device as valid commands, and the w pand h o l d pins function as normal control pins. the w pand h o l d pins should be externally pulled-high to avoid erroneous or unwanted device operation. the reset command has no effect on the qe bit. the qe bit defaults to the logical ?0? state when devices are initially shipped from atmel. bit (1) name type (2) description 7 qe quad enable r/w 0 quad-input/output commands and operation disabled. 1 quad-input/output commands and operation enabled ( wp and hold disabled). 6:0 res reserved for future use r 0 reserved for future use. 43 8718a?dflash?04/10 at25dq321a [preliminary] figure 11-4. read configuration register 11.5 write configuration register the write configuration register command is used to modify the qe bit of the non-volatile configuration register. before the write configuration register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write configuration register command, the cs pin must first be asserted and the opcode of 3eh must be clocked into the device followed by one byte of data. the one byte of data consists of the qe bit value and seven don?t care bits ( table 11-6 ). any additional data clocked into the device will be ignored. when the cs pin is deasserted, the qe bit of the configuration register will be modified within a time of t wrcr , and the wel bit in the status register will be reset back to a logical ?0?. the complete one byte of data must be clocked into the device before the c s pin is deasserted, and the c s pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the value of the configuration register will not change, and the wel bit in the status register will be reset back to the logical ?0? state. the configuration register is a non-volatile register and is subject to the same program/erase endurance characteristics of the main memory array. the programming of the configuration register is internally self-timed and should take place in a time of t wrcr. while the configuration register is being updated, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t wrcr time to determine if the configuration register has completed the programming cycle. at some point before the programming cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. table 11-6. write configuration register format so si sck cs msb 23 1 0 00111111 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 opcode msb msb xxxxxx dx x d msb xxxxxx x d configuration register out configuration register out high-impedance bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 qexxxxxxx 44 8718a?dflash?04/10 at25dq321a [preliminary] figure 11-5. write configuration register 12. other commands and functions 12.1 reset in some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. the reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state. since the need to reset the device is immediate, the write enable command does not need to be issued prior to the reset command being issued. therefore, the reset command operates independently of the state of the wel bit in the status register. the reset command can only be executed if the command has been enabled by setting the reset enabled (rste) bit in the status register to a logical ?1?. if the reset command has not been enabled (the rste bit is in the logical ?0? state), then any attempts at executing the reset command will be ignored. to perform a reset, the cs pin must first be asserted and the opcode of f0h must be clocked into the device. no address bytes need to be clocked in, but a confirmation byte of d0h must be clocked into the device immediately after the opcode. any additional data clocked into the device after the confirmation byte will be ignored. when the cs pin is deasserted, the program or erase operation currently in progress will be terminated within a time of t rst . since the program or erase operation may not complete before the device is reset, the contents of the page being programmed or the block being erased cannot be guaranteed to be valid. the reset command has no effect on the states of the sector protection registers, the sector lockdown registers, the configuration register, or the sprl, rste, and sle bits in the status register. the wel, ps, and es bits of the status register, however, will be reset back to their default states. if a reset operation is performed while a sector is erase suspended, the suspend operation will abort, and the contents of the block being erased in the suspended sector will be left in an undefined state. if a reset is performed while a sector is program suspended, the suspend operation will abort, and the contents of the page that was being programmed and subsequently suspended will be undefined. the remaining pages in the 64-kbyte sector will retain their previous contents. the complete opcode and confirmation byte must be clocked into the device before the cs pin is deasserted, and the c s pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no reset operation will be performed. so si sck cs msb 23 1 0 0011111 67 5 4 opcode 10 11 9 81415 13 12 0 msb dxxxxxx x configuration register in high-impedance 45 8718a?dflash?04/10 at25dq321a [preliminary] figure 12-1. reset 12.2 read manufacturer and device id identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the vendor specific extended device information. the read manufacturer and device id command is limited to a maximum clock frequency of f clk . since not all flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the application can be identified properly. once the identification process is complete, the application can then increase the clock frequency to accommodate specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte output will be the extended device information (edi) string length, which will be 01h indicating that one byte of edi data follows. after the one byte of edi data is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. as indicated in the jedec standard, reading the edi string length and any subsequent data is optional. deasserting the c s pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the c s pin can be deasserted at any time and does not require that a full byte of data be read. so si sck cs 0 6 % 2 3 & 2 ' ( & 2 1 ) , 5 0 $ 7 , 2 1 % < 7 ( , 1 0 6 % + , * + , 0 3 ( ' $ 1 & ( 46 8718a?dflash?04/10 at25dq321a [preliminary] table 12-1. manufacturer and device id information table 12-2. manufacturer and device id details table 12-3. figure 12-2. read manufacturer and device id byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 88h 3 device id (part 2) 00h 4 [optional to read] extended device information (edi) string length 01h 5 [optional to read] edi byte 1 00h data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for atmel) 00011111 device id (part 1) family code density code 87h family code: 100 (quad-i/o or rapid4 ? ) density code: 00111 (32-mbit) 10000111 device id (part 2) sub code product variant 00h sub code: 000 (quad-i/o series) product variant: 00000 (standard version) 00000000 byte number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details 1 rfu device revision 00h rfu: reserved for future use density code: 00000 (initial version) 00000000 so si sck cs 6 0 9fh 8 7 46 opcode 1fh 86h 00h 01h 00h manufacturer id device id byte 1 device id byte 2 edi string length edi data byte 1 high-impedance 14 16 15 22 24 23 38 40 39 30 32 31 note: each transition shown for si and so represents one byte (8 bits) 47 8718a?dflash?04/10 at25dq321a [preliminary] 12.3 deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consumption state called the deep power-down mode. when the device is in the deep power-down mode, all commands including the read status register command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the c s pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the c s pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power-cycle. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. figure 12-3. deep power-down so si sck cs 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 6 w d q g e \ 0 r g h & x u u h q w $ f w l y h & x u u h q w ' h h s 3 r z h u ' r z q 0 r g h & x u u h q w w ( ' 3 ' i cc 48 8718a?dflash?04/10 at25dq321a [preliminary] 12.4 resume from deep power-down in order to exit the deep power-down mode and resume normal device operation, the resume from deep power- down command must be issued. the resume from deep power-down command is the only command that the device will recognized while in the deep power-down mode. to resume from the deep power-down mode, the c s pin must first be asserted and opcode of abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power-down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the c s pin is deasserted, or if the c s pin is not deasserted on a byte boundary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. figure 12-4. resume from deep power-down so si sck cs i cc 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( ' h h s 3 r z h u ' r z q 0 r g h & x u u h q w $ f w l y h & x u u h q w 6 w d q g e \ 0 r g h & x u u h q w w 5 ' 3 ' 49 8718a?dflash?04/10 at25dq321a [preliminary] 12.5 hold the hold pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. therefore, if an erase cycle is in progress, asserting the h o l d pin will not pause the operation, and the erase cycle will continue until it is finished. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the h o l d pin during the sck low pulse. if the h o l d pin is asserted during the sck high pulse, then the hold mode won?t be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pin will be in a high-impedance state. in addition, both the si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the h o l d pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, then the hold mode won?t end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the wel bit in the status register back to the logical ?0? state. figure 12-5. hold mode hold sck cs + r o g + r o g + r o g 50 8718a?dflash?04/10 at25dq321a [preliminary] 13. electrical specifications 13.1 absolute maximum ratings* 13.2 dc and ac operating range temperature under bias ................. -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these ratings or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the "absolute maximum ratings" are intended to accommo- date short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time. storage temperature...................... -65 ? c to +150 ? c all input voltages (including nc pins) with respect to ground ......................-0.6v to +4.1v all output voltages with respect to ground ..............-0.6v to v cc + 0.5v at25dq321a operating temperature (case) ind. -40 ? cto85 ? c v cc power supply 2.7v to 3.6v 13.3 dc characteristics symbol parameter condition min typ max units i sb standby current cs, wp, hold = v cc , all inputs at cmos levels 25 50 a i dpd deep power-down current cs, wp, hold = v cc , all inputs at cmos levels 510a i cc1 active current, read operation f = 100 mhz; i out = 0 ma; cs = v il ,v cc = max 12 19 ma f = 85 mhz; i out = 0 ma; cs = v il ,v cc = max 10 17 f = 66 mhz; i out = 0 ma; cs = v il ,v cc = max 814 f = 50 mhz; i out = 0 ma; cs = v il ,v cc = max 712 f = 33 mhz; i out = 0 ma; cs = v il ,v cc = max 610 f = 20 mhz; i out = 0 ma; cs = v il ,v cc = max 58 i cc2 active current, program operation cs = v cc ,v cc = max 10 20 ma i cc3 active current, erase operation cs = v cc ,v cc = max 12 20 ma i li input leakage current v in = cmos levels 1 a 51 8718a?dflash?04/10 at25dq321a [preliminary] 13.4 ac characteristics ? maximum clock frequencies i lo output leakage current v out = cmos levels 1 a v il input low voltage 0.3 x v cc v v ih input high voltage 0.7 x v cc v v ol output low voltage i ol = 1.6 ma; v cc = min 0.4 v v oh output high voltage i oh = -100 a; v cc = min v cc - 0.2v v symbol parameter min max units rapids and spi operation f max maximum clock frequency for all operations ? rapids operation only (excluding 03h, 0bh, 3bh, 6bh, and 9f opcodes) 100 mhz f clk maximum clock frequency for all operations (excluding 03h opcode) 85 mhz f rdlf maximum clock frequency for 03h opcode (read array ? low frequency) 33 mhz f rddo maximum clock frequency for 3bh opcode (dual-output read) 70 mhz f rdqo maximum clock frequency for 6bh opcode (quad-output read) 70 mhz 13.3 dc characteristics (continued) symbol parameter condition min typ max units 52 8718a?dflash?04/10 at25dq321a [preliminary] 13.5 ac characteristics ? all other parameters note: 1. not 100% tested (value guaranteed by design and characterization). 2. 15 pf load at frequencies above 70 mhz, 30 pf otherwise. 3. only applicable as a constraint for the write status register byte 1 command when sprl = 1. symbol parameter min max units t clkh clock high time 4.3 ns t clkl clock low time 4.3 ns t clkr (1) clock rise time, peak-to-peak (slew rate) 0.1 v/ns t clkf (1) clock fall time, peak-to-peak (slew rate) 0.1 v/ns t csh chip select high time 35 ns t csls chip select low setup time (relative to clock) 5 ns t cslh chip select low hold time (relative to clock) 5 ns t cshs chip select high setup time (relative to clock) 5 ns t cshh chip select high hold time (relative to clock) 5 ns t ds data in setup time 2ns t dh data in hold time 1ns t dis (1) output disable time 5ns t v (2) output valid time 5ns t oh output hold time 2ns t hls hold low setup time (relative to clock) 5 ns t hlh hold low hold time (relative to clock) 5 ns t hhs hold high setup time (relative to clock) 5 ns t hhh hold high hold time (relative to clock) 5 ns t hlqz (1) hold low to output high-z 5ns t hhqx (1) hold high to output low-z 5ns t wps (1)(3) write protect setup time 20 ns t wph (1)(3) write protect hold time 100 ns t secp (1) sector protect time (from chip select high) 20 ns t secup (1) sector unprotect time (from chip select high) 20 ns t lock (1) sector lockdown and freeze sector lockdown state time (from chip select high) 200 s t edpd (1) chip select high to deep power-down 1 s t rdpd (1) chip select high to standby mode 8s t rst reset time 30 s 53 8718a?dflash?04/10 at25dq321a [preliminary] 13.6 program and erase characteristics notes: 1. maximum values indicate worst-case performance after 100,000 erase/program cycles. 2. not 100% tested (value guaranteed by design and characterization). 13.7 power-up conditions 13.8 input test waveforms and measurement levels 13.9 output test load symbol parameter min typ max units t pp (1) page program time (256 bytes) 1.5 5.0 ms t bp byte program time 20 s t blke (1) block erase time 4 kbytes 50 200 ms 32 kbytes 250 600 64 kbytes 400 950 t chpe (1)(2) chip erase time 36 56 sec t susp suspend time program 10 20 s erase 25 40 t res resume time program 10 20 s erase 12 20 t otpp (1) otp security register program time 200 500 s t wrsr (2) write status register time 200 ns t wrcr write configuration register time 15 35 ms symbol parameter min max units t vcsl minimum v cc to chip select low time 100 s t puw power-up device delay before program or erase allowed 10 ms v por power-on reset voltage 1.8 2.2 v ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2 ns (10% to 90%) device under test 15 pf (frequencies above 70 mhz) or 30pf 54 8718a?dflash?04/10 at25dq321a [preliminary] 14. ac waveforms figure 14-1. serial input timing figure 14-2. serial output timing figure 14-3. wp timing for write status register byte 1 command when sprl = 1 so si sck cs 0 6 % + , * + , 0 3 ( ' $ 1 & ( 0 6 % / 6 % w & 6 / 6 w & / . + w & / . / w & 6 + 6 w & 6 + + w ' 6 w ' + w & 6 / + w & 6 + so si sck cs w 9 w & / . + w & / . / w ' , 6 w 9 w 2 + so si sck wp cs + , * + , 0 3 ( ' $ 1 & ( 0 6 % ; w : 3 6 w : 3 + / 6 % 2 ) : 5 , 7 ( 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 ' $ 7 $ % < 7 ( 0 6 % 2 ) : 5 , 7 ( 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 % < 7 ( 2 3 & 2 ' ( 0 6 % 2 ) 1 ( ; 7 2 3 & 2 ' ( 55 8718a?dflash?04/10 at25dq321a [preliminary] figure 14-4. hold timing ? serial input figure 14-5. hold timing ? serial output so si hold sck cs w + + + w + / 6 w + / + w + + 6 + , * + , 0 3 ( ' $ 1 & ( so si hold sck cs w + + + w + / 6 w + / 4 = w + / + w + + 6 w + + 4 ; 56 8718a?dflash?04/10 at25dq321a [preliminary] 15. ordering information 15.1 ordering code detail 15.2 green package options (pb/halide-free/rohs compliant) note: the shipping carrier option code is not marked on the devices. atmel designator product family device density interface shipping carrier option device grade package option 1 = serial 16 = 16-megabit b = bulk (tubes) y = bulk (trays) t = tape and reel h = green, nipdau lead finish industrial temperature range (-40c to +85c) 53 = 16-lead 0.300? wide soic s = 8-lead, 0.208? wide soic ma = 8-pad, 5 x 6 x 0.300? wide soic AT25DQ321A-53H-B ordering code package lead (pad) finish operating voltage max. freq. (mhz) operation range at25dq321a-mh-b at25dq321a-mh-t 8ma1 nipdau 2.7v to 3.6v 100 industrial (-40c to +85c) at25dq321a-sh-b at25dq321a-sh-t 8s1 AT25DQ321A-53H-B at25dq321a-53h-t 16s package type 8ma1 8-pad ( 5x6x0.6mm body), thermally enhanced plastic ultra thin dual flat no lead package (udfn) 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 16s 16-lead, 0.300? wide, plastic gull wing small outline package (soic) 57 8718a?dflash?04/10 at25dq321a [preliminary] 16. packaging information 16.1 8ma1 ? udfn package drawing contact: packagedrawings@atmel.com drawing no. rev. title gpc notes: 1. this package conforms to jedec reference mo-229, saw singulation. 2. the terminal #1 id is a laser-marked feature. 8ma1 d 4/15/08 8ma1, 8-pad (5 x 6 x 0.6 mm body), thermally enhanced plastic ultra thin dual flat no lead package (udfn) yfg top view side view common dimensions (unit of measure = mm) symbol min nom max note 0.45 0.00 0.35 4.90 3.80 5.90 3.20 0.50 0.00 0.20 a a1 b c d d2 e e2 e l y k 0.55 0.02 0.40 0.152 ref 5.00 4.00 6.00 3.40 1.27 0.60 ? ? 0.60 0.05 0.48 5.10 4.20 6.10 3.60 0.75 0.08 ? pin 1 id e d a1 a y c bottom view e2 d2 l b e 1 2 3 4 8 7 6 5 pin #1 notch (0.20 r) k pin #1 chamfer (c 0.35) option a (option b) 58 8718a?dflash?04/10 at25dq321a [preliminary] 16.2 8s1 ? jedec soic package drawing contact: packagedrawings@atmel.com drawing no. rev. title gpc 8s1 e 12/11/09 8s1, 8-lead, (0.150? wide body), plastic gull wing outline (jedec soic) swb ? ? ? ? ? ? ? 1.27 bsc ? ? 1.75 0.25 0.51 0.25 5.05 3.99 6.20 1.27 8? common dimensions (unit of measure = mm) symbol min nom max note 1.35 0.10 0.31 0.17 4.80 3.81 5.79 0.40 0? a a1 b c d e1 e e l notes: 1. these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. e 1 2 3 4 8 7 6 5 gnd nc nc nc sda scl nc v cc ? c e1 l a b a1 e d end view top view side view 59 8718a?dflash?04/10 at25dq321a [preliminary] 16.3 16s ? soic package drawing contact: packagedrawings@atmel.com drawing no. rev. title notes: 1. this drawing is for general information only; refer to jedec drawing ms-013, variation aa for additional information. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. dimension e does not include inter-lead flash or protrusion. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. l is the length of the terminal for soldering to a substrate. 16s a 11/02/05 16s , 16-lead, 0.300" wide body, plastic gull wing small outline package (soic) end view top view side view common dimensions (unit of measure = mm) symbol min nom max note 2.35 0.10 0.31 0.40 0.20 a a1 b d e h l e c ? ? ? 10.30 bsc 7.50 bsc 10.30 bsc ? 1.27 bsc 2.65 0.30 0.51 1.27 0.33 2 3 4 h e n 1 a1 b e a d e l c 60 8718a?dflash?04/10 at25dq321a [preliminary] 17. revision history doc. rev. date comments 8718a 4/2010 initial document release 8718a?dflash?04/10 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support dataflash@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or inciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to s pecifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifica lly provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2010 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, dataflash ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. |
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